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ASAHI KASEI
[AK2546]
AK2546 7 channel T1 Transceiver
FEATURE * 7ch short haul T1 transceiver * Jitter Tolerance: Compliant with GR-499 Category I, II * Transmitter Pulse Shape: Compliant with GR-499 * Loss of Signal Detection * Selectable Signal Polarity * Local/Remote Loopback * Parallel Microprocessor Interface * Single 3.3V5% Operation * Low Power Consumption (105mW/ch: Typ) * Pin-to-pin compatible with AK2548 (7 channel E1 transceiver) * Small Plastic Package 144pin LQFP
BLOCK DIAGRAM
MCLK CLKSEL RESET TEST1-5 R /W (WR) AD7-AD0
CLKGEN CONTROL
AS(ALE) DS(RD) CS BTS INT LOS1
TRANSCEIVER 1
RTIP1 RRING1 TTIP1
LOS
Remote Loopback
Local Loopback
RECOVER
RCLK1 RPOS RNEG1 TCLK1 TPOS TNEG1
SHAPER
TRING1
RTIP2-7 RRING2-7 TTIP2-7 TRING2-7
TRANSCEIVER 2-7
LOS2-7 RCLK2-7 RPOS2-7 RNEG2-7 TCLK2-7 TPOS2-7 TNEG2-7
7 Channel T1 Transceiver Block Diagram
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ASAHI KASEI
[AK2546]
GENERAL DESCRIPTION The AK2546 is the 7 channel short haul T1 transceiver for a SONET MUX, M13 MUX, etc. It includes seven independent transmitters, clock and data recovery, LOS detector, control circuit in one LQFP-144 package which saves space, power consumption and the board design time. Internally generated transmit pulse provides the appropriate pulse shape for line length ranging from 0 to 655 feet from a DSX-1 cross connect.
PIN ASSIGNMENTS
AVSS8 TTIP7 TVSS7 TVDD7 TRING7 AVSS7 TTIP6 TVSS6 TVDD6 TRING6 AVSS6 TTIP5 TVSS5 TVDD5 TRING5 AVSS5 TTIP4 TVSS4 TVDD4 TRING4 AVSS4 TTIP3 TVSS3 TVDD3 TRING3 AVSS3 TTIP2 TVSS2 TVDD2 TRING2 AVSS2 TTIP1 TVSS1 TVDD1 TRING1 AVSS1 TCLK7 TPOS7 TNEG7 RCLK7 RPOS7 RNEG7 TCLK6 TPOS6 TNEG6 RCLK6 RPOS6 RNEG6 IOVDD2 IOVSS2 TAVDD2 TAVSS2 TCLK5 TPOS5 TNEG5 RCLK5 RPOS5 RNEG5 DAVSS2 DVSS2 DVDD2 LOS7 LOS6 LOS5 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
(TOP VIEW)
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R/W(WR) AS(ALE) DS(RD) CS INT PVDD MCLK PVSS RAVSS2 RAVDD2 RESET RRING7 RTIP7 BTS RRING6 RTIP6 TEST5 RRING5 RTIP5 TEST4 BVSS BGREF BVDD TEST3 RRING4 RTIP4 TEST2 RRING3 RTIP3 CLKSEL RRING2 RTIP2 TEST1 RRING1 RTIP1 RAVSS1
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TCLK1 TPOS1 TNEG1 RCLK1 RPOS1 RNEG1 TCLK2 TPOS2 TNEG2 RCLK2 RPOS2 RNEG2 IOVDD1 IOVSS1 TAVDD1 TAVSS1 TCLK3 TPOS3 TNEG3 RCLK3 RPOS3 RNEG3 DAVSS1 DVSS1 DVDD1 TCLK4 TPOS4 TNEG4 RCLK4 RPOS4 RNEG4 LOS1 LOS2 LOS3 LOS4 RAVDD1
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ASAHI KASEI
[AK2546]
PIN CONDITION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Pin Name TCLK7 TPOS7 TNEG7 RCLK7 RPOS7 RNEG7 TCLK6 TPOS6 TNEG6 RCLK6 RPOS6 RNEG6 IOVDD2 IOVSS2 TAVDD2 TAVSS2 TCLK5 TPOS5 TNEG5 RCLK5 RPOS5 RNEG5 DAVSS2 DVSS2 DVDD2 LOS7 LOS6 LOS5 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
I/O I I I O O O I I I O O O I I I I I I I O O O I I I O O O I/O I/O I/O I/O I/O I/O I/O I/O
Pin Type CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power Power CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
AC Load
DC Load
Comments
15pF 15pF 15pF
15pF 15pF 15pF
15pF 15pF 15pF
15pF 15pF 15pF 50pF 50pF 50pF 50pF 50pF 50pF 50pF 50pF
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ASAHI KASEI
[AK2546]
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Pin Name R/W(WR) AS(ALE) DS(RD) CS INT PVDD MCLK PVSS RAVSS2 RAVDD2 RESET RRING7 RTIP7 BTS RRING6 RTIP6 TEST5 RRING5 RTIP5 TEST4 BVSS BGREF BVDD TEST3 RRING4 RTIP4 TEST2 RRING3 RTIP3 CLKSEL RRING2 RTIP2 TEST1 RRING1 RTIP1 RAVSS1
I/O I I I I O I I I I I I I I I I I I I I I I O I I I I I I I I I I I I I I
Pin Type CMOS CMOS CMOS CMOS Open drain Power CMOS Power Power Power CMOS Analog Analog CMOS Analog Analog CMOS Analog Analog CMOS Power Analog Power CMOS Analog Analog CMOS Analog Analog CMOS Analog Analog CMOS Analog Analog Power
AC Load
DC Load
Comments
PMOS Open drain
Note1)
Note1) 12k 1% accuracy Note1)
Note2)
Note1)
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ASAHI KASEI
[AK2546]
Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
Pin Name RAVDD1 LOS4 LOS3 LOS2 LOS1 RNEG4 RPOS4 RCLK4 TNEG4 TPOS4 TCLK4 DVDD1 DVSS1 DAVSS1 RNEG3 RPOS3 RCLK3 TNEG3 TPOS3 TCLK3 TAVSS1 TAVDD1 IOVSS1 IOVDD1 RNEG2 RPOS2 RCLK2 TNEG2 TPOS2 TCLK2 RNEG1 RPOS1 RCLK1 TNEG1 TPOS1 TCLK1
I/O I O O O O O O O I I I I I I O O O I I I I I I I O O O I I I O O O I I I
Pin Type Power CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power Power CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
AC Load 15pF 15pF 15pF 15pF 15pF 15pF 15pF
DC Load
Comments
15pF 15pF 15pF
15pF 15pF 15pF
15pF 15pF 15pF
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ASAHI KASEI
[AK2546]
Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Pin Name AVSS1 TRING1 TVDD1 TVSS1 TTIP1 AVSS2 TRING2 TVDD2 TVSS2 TTIP2 AVSS3 TRING3 TVDD3 TVSS3 TTIP3 AVSS4 TRING4 TVDD4 TVSS4 TTIP4 AVSS5 TRING5 TVDD5 TVSS5 TTIP5 AVSS6 TRING6 TVDD6 TVSS6 TTIP6 AVSS7 TRING7 TVDD7 TVSS7 TTIP7 AVSS8
I/O I O I I O I O I I O I O I I O I O I I O I O I I O I O I I O I O I I O I
Pin Type Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power
AC Load
DC Load
Comments driver output
driver output driver output
driver output driver output
driver output driver output
driver output driver output
driver output driver output
driver output driver output
driver output
Note1 ) Should be connected to VSS externally. Note2 ) Should be connected to VDD externally
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ASAHI KASEI PIN DESCRIPTIONS
Pin Name TTIP1-7 TRING1-7 TPOS1-7 TNEG1-7 TCLK1-7 RTIP1-7 RRING1-7 RPOS1-7 RNEG1-7 RCLK1-7 LOS1-7 I/O O O I I I I I O O O O Transmit Tip/Ring Output Bipolar output over transmit transformer Transmit Positive/Negative Data Input Input on the falling edge of TCLK Transmit Clock Input Receive Tip/Ring Input Bipolar Input over receive transformer Receive Positive/Negative Data Output Output on the falling edge of RCLK Receive Clock Output recovered from receive data input Loss of signal output Output "high" when detect loss of signal LOSx output is not masked by MLOSx register. TVDD1-7 TVSS1-7 AVSS1-8 Common Block MCLK AS(ALE) INT I I O 1.544MHz or 24.704MHz External Reference Clock Input Address Select(Address Latch Enable) Input Interrupt Output(PMOS open drain, should be tied to GND through a resistor), Active High, INT output goes "high" when the alarm is reported to any one of LOSx, LOTCx or LOMC registers. This pin can be masked by MLOSx, MLOTCx or MLOMC registers. DS(RD) R/W (WR) CS BTS I I I I Data Strobe(Read Enable) Input Read/Write(Write Enable) Input Chip Select Input Bus Type Select Input BTS="H" : Motorola Mode BTS="L" : Intel Mode AD0-AD7 CLKSEL I/O I Address/Data Input/Output Used for read/write internal registers. MCLK Select Input CLKSEL="H":1.544MHz CLKSEL="L":24.704MHz RESET I Reset Input Active "Low" input pulse over 200ns initializes the internal circuit and forces RPOSx/RNEGx output "low" and LOSx output "high". Positive Power Supply for the Transmit Driver Negative Power Supply for the Transmit Driver Analog ground Function
[AK2546]
Comment
T1 Transceiver
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ASAHI KASEI
[AK2546]
Pin Name TEST1,3-5 TEST2 TAVDD1,2 TAVSS1,2 RAVDD1,2 RAVSS1,2 DVDD1,2 DVSS1,2 DAVSS1,2 IOVDD1,2 IOVSS1,2 BVDD BVSS PVDD PVSS BGREF
I/O I I
Function Factory Use. Should be connected to VSS externally. Factory Use. Should be connected to VDD externally. Positive Power Supply for the analog circuitry in the transmitters Negative Power Supply for the analog circuitry in the transmitters Positive Power Supply for the digital circuitry in the transmitters Negative Power Supply for the digital circuitry in the transmitters Positive Power Supply for Digital Negative Power Supply for Digital Ground for Digital Positive Power Supply for I/O Negative Power Supply for I/O Positive Power Supply for Reference Circuit Negative Power Supply for Reference Circuit Positive Power Supply for PLL Negative Power Supply for PLL Bandgap Reference Output. 12k 1% external register should be connected across this pin and VSS.
Comment
Common block
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ASAHI KASEI
[AK2546]
ABSOLUTE MAXIMUM RATINGS
Parameter DC Supply Input Voltage
Symbol VDD VIN1 VIN2
Min -0.3 -0.3 -3 -55
Typ
Max 6.5 VDD+0.3 VDD+0.3 10 130
Units V V V mA C
Condition
Apply to except for RTIPx, RRINGx Apply to RTIPx, RRINGx
Input Current Storage Temperature
IIN Tstg
Note) All voltages with respect to ground. : All negative voltage pins = 0V. VDD apply to all positive voltage pins.
RECOMMENDED OPERATING CONDITIONS
Parameter DC Supply Ambient Operating Temperature
Symbol VDD Ta
min 3.135 -40
typ 3.3 25
max 3.465 +85
Units V C
Condition 3.3V5%
Note) All voltages with respect to ground. : All negative voltage pins = 0V. VDD apply to all positive voltage pins.
ELECTORICAL CHARACTERISTICS
DC CHARACTERISTICS
Parameter Power Consumption(/ch) Digital High-Level Output Voltage Digital Low-Level Output Voltage Digital High-Level Input Voltage Digital Low-Level Input Voltage Input Leak Current Output Current Symbol PD VOH VOL VIH VIL Ii IOL 1.0 0.7VDD 0.3VDD 10 0.9VDD 0.4 min typ 105 max 260 Units Condition mW Note1 V V V V A mA INT pin IOH=-40A IOL=500A
Note1: typ : 50% mark, Room temp., VDD 3.3V, line length 399feet, Load 100 max: 100% mark, Temp./VDD in all range, line length 655feet, Load 100 Not include any other load (ex. External pull up register) except lines.
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ASAHI KASEI
[AK2546]
RECEIVER
Receiver characteristics are guaranteed on the conditions as shown below. VDD=3.3V5%, VSS, GND=0V, Ta=-40~85C, MCLK frequency: 1.544MHz100ppm, 24.704MHz100ppm, Bipolar input frequency: 1.544MHz130ppm(reference input level: 3V0p20%) Parameter Sensitivity Loss of Signal Threshold Allowable Consecutive Zero before LOS S/X tolerance Generated Jitter Low pulse density immunity Jitter Tolerance 30 Symbol Min -6 0.35 170 0.5 175 0.7 180 12 Typ Max Units dB V bits dB Note3 nspp Note4 Condition Note1 Note2
1/16 GR-499 Category I,II
Mark
Note1: Relative value to the reference level. Compare at 772kHz with All Mark Pattern. Note2: Level at the chip side of transformer. Loss of signal is logical AND between an analog loss of Signal monitors input level and a digital loss of signal check recovered data stream. Note3: PN20 and AMI 1/8 Mark pattern input. Noise frequency is 770kHz. Note4: PN20 pattern input.
JITTER TOLERANCE
100 Jitter Amplitude(UIpp) 10 1 0.1 0.01 1 10 100 1000 10000 100000 Jiiter Frequency(Hz)
GR-499 Category II
GR-499 Category I
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ASAHI KASEI
[AK2546]
TRANSMITTER
Transmitter characteristics are guaranteed on the conditions as shown below. VDD=3.3V5%, VSS, GND=0V,Ta=-40~85C, MCLK frequency: 1.544MHz100ppm, 24.704MHz100ppm Parameter Output Pulse Shape Output Pulse Amplitude Output Pulse Imbalance Output Jitter 10Hz-8kHz 10Hz-40kHz 8kHz-40kHz Broad Band Power Levels@772kHz Power Levels @1.544MHz Note1: Measured at the DSX terminated with 100. Note2: Amplitude at the pulse center to normalize to unity. Turns Ratio and DCR are recommended value. Note3: Measured in a 2kHz band width around the specified frequency. Transmit all mark pattern. Note4: Compare to the power at 772kHz 12.6 15 2.5 3.0 3.5 0.4 0.02 0.025 0.025 0.05 17.9 -29 dBm Note3 dB Note3, Note4 V0p dB UIpp Symbol Min Typ Max Units Condition
GR-499,Note1
Note1, Note2
ISOLATED PULSE MASK (GR-499)
Normalized Amplitude 1.5 1 0.5 0 -0.5 -1 -1 -0.5 0 0.5 1 1.5 Time, in Unit Intervals
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ASAHI KASEI
[AK2546]
AC CHARACTERISTICS (Clock/Data)
Parameter Clock Frequency Clock Pulse Width Clock Pulse Width Duty Cycle Setup/Hold Time MCLK MCLK TCLK RCLK RCLK TCLK RCLK RPOS RNEG Setup/Hold Time TCLK TPOS TNEG Rise Time RCLK RPOS RNEG Fall Time TCLK TPOS TNEG Note1) Duty Cycle:(tpwho/( tpwho+tpwlo))x100% Note2) Drive 15pF Load Capacitance tf 40 ns Refer to Fig.3 Note2 tr 100 ns Refer to Fig.3 Note2 tsu2 th2 50 ns Refer to Fig.2 tsu1 th1 150 ns Refer to Fig.1 Symbol Fci tpwhi tpwli tpwho tpwlo 50 % Note1 324 ns Refer to Fig.1 Min Typ Max Units Condition
1.543846 1.544000 1.544154 24.70153 24.70400 24.70647 324
MHz 100ppm ns Refer to Fig.2
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ASAHI KASEI
[AK2546]
tpwho 50%
tpwlo 50% tsur 50% thr
RCLK
RPOS/RNEG
50%
Fig.1 Receiver Timing
tpwhi tpwli
TCLK
50% tsut
50% tht
50%
TPOS/TNEG
50%
Fig.2 Transmitter Timing
tr 90% 10% 90%
tf
10%
Fig.3 Rise and Fall Times (RCLK, RPOS, RNEG, TCLK, TPOS, TNEG)
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ASAHI KASEI
[AK2546]
AC CHARACTERISTICS (Parallel Port)
Parameter Read/Write Cycle Motorola Mode Address Setup Time Address Hold Time AS to DS Delay Time DS to AS Delay Time Read Data Delay Time Read Data Hold Time R/W Setup Time R/W Hold Time CS Setup Time CS Hold Time Write Data Setup Time Write Data Hold Time DS Pulse Width AS Pulse Width Address Invalid to DS Delay Time Intel Mode Address Setup Time Address Hold Time ALE to WR Delay Time WR to ALE Delay Time RD to ALE Delay Time Read Data Delay Time Read Data Hold Time CS Setup Time CS Hold Time Write Data Setup Time Write Data Hold Time RD Pulse Width WR Pulse Width ALE Pulse Width Address Invalid to RD Delay Time t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 10 10 20 20 20 -- -- 10 15 40 20 100 100 20 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40 20 -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 10 10 20 20 -- -- 10 10 10 15 40 20 100 20 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40 20 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol tcyc Min 250 Typ Max Units Condition ns
Notes) CL= 50pF on AD0-AD7. All of the timing is specified at 50%VDD.
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ASAHI KASEI
[AK2546]
Motorola Mode(READ)
CS t9 t13 t14 AS t5 t10
DS
t4 t6
t1
t2 t15 Data
AD7-0 R/W
Address
t7
t8
Motorola Mode(WRITE)
t9 t13 DS t14 AS t3 t4 t10
CS
t1
t2
t11 Data t7
t12
AD7-0 R/W
Address
t8
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ASAHI KASEI
[AK2546]
Intel Mode(READ)
CS t28 t29
WR t34 ALE t21 AD7-0 RD t22 Data t35 t32 t27 t26 t25
Address
Intel Mode(WRITE)
CS
t28 t33 t34 t23
t29
WR
t24
ALE t21 AD7-0 RD t22 t30 Data t31
Address
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ASAHI KASEI
[AK2546]
REGISTER DESCRIPTION
REGISTER MAP
*A7-A4="0" Address
A3 A2 A1 A0
Bit7 Bit6 Bit5
Function
Bit4 Bit3 Bit2 Bit1 Bit0
Status Register (READ ONLY)
0 0
0 0
0 0
0 1
LOS7 (1) LOTC7 (1)
LOS6 (1) LOTC6 (1)
LOS5 (1) LOTC5 (1)
LOS4 (1) LOTC4 (1)
LOS3 (1) LOTC3 (1)
LOS2 (1) LOTC2 (1)
LOS1 (1) LOTC1 (1)
0
LOMC (1)
Mask Control Register (WRITE/READ)
0 0
0 0
1 1
0 1
MLOS7 (1) MLOTC7 (1)
MLOS6 (1) MLOTC6 (1)
MLOS5 (1) MLOTC5 (1)
MLOS4 (1) MLOTC4 (1)
MLOS3 (1) MLOTC3 (1)
MLOS2 (1) MLOTC2 (1)
MLOS1 (1) MLOTC1 (1)
RDEN (0) MLOMC (1)
Channel Control Register (WRITE/READ)
0 0 1 1 1 1 1
1 1 0 0 0 0 1
1 1 0 0 1 1 0
0 1 0 1 0 1 0
LENG31 (0) LENG32 (0) LENG33 (0) LENG34 (0) LENG35 (0) LENG36 (0) LENG37 (0)
LENG21 (0) LENG22 (0) LENG23 (0) LENG24 (0) LENG25 (0) LENG26 (0) LENG27 (0)
LENG11 (0) LENG12 (0) LENG13 (0) LENG14 (0) LENG15 (0) LENG16 (0) LENG17 (0)
RLOOP1 (0) RLOOP2 (0) RLOOP3 (0) RLOOP4 (0) RLOOP5 (0) RLOOP6 (0) RLOOP7 (0)
LLOOP1 (0) LLOOP2 (0) LLOOP3 (0) LLOOP4 (0) LLOOP5 (0) LLOOP6 (0) LLOOP7 (0)
POLN1 (1) POLN2 (1) POLN3 (1) POLN4 (1) POLN5 (1) POLN6 (1) POLN7 (1)
MSK1 (1) MSK2 (1) MSK3 (1) MSK4 (1) MSK5 (1) MSK6 (1) MSK7 (1)
PD1 (1) PD2 (1) PD3 (1) PD4 (1) PD5 (1) PD6 (1) PD7 (1)
*Other address is reserved. * Initial value is in ( ). *"<>" show I/O pin name. Address A0-A3 should be input via AD0-AD3 pins.
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ASAHI KASEI
[AK2546]
STATUS REGISTER Symbol
LOSx (x=1 to 7) LOTCx (x=1 to 7) LOMC
Description
Loss of signal alarm for channel x. Read only register. When the loss of signal is detected, LOSx is set High. Loss of TCLK alarm for channel x. Read only register. When the loss of TCLKx is detected, LOTCx is set High. Loss of MCLK alarm. Read only register. When the loss of MCLK is detected, LOMC is set High.
MASK CONTROL Symbol
MLOSx (x=1 to 7)
Description Mask loss of signal alarm for channel x. MLOSx is active-high to prevent LOSx from setting INT output "high". It is possible to read LOSx register regardless of the status of MLOSx. Initial value is "high". Mask loss of TCLK alarm for channel x. MLOTCx is active-high to prevent LOTCx from setting INT output "high". It is possible to read LOTCx register regardless of the status of MLOTCx. Initial value is "high". Mask loss of MCLK alarm. MLOMC is active-high to prevent LOMC from setting INT output "high". It is possible to read LOMC register regardless of the status of MLOMC. Initial value is "high". When the loss of MCLK is detected, LOSx register and LOSx pins are set "high" at the same time. Therefore all MLOSx register must be set "high" to prevent loss of MCLK from setting INT output. In this case, LOMC can be read.
MLOTCx (x=1 to 7)
MLOMC
CHANNEL CONTROL REGISTER Symbol
LENGyx
Description
RLOOPx/ LLOOPx POLNx PDx
MSKx RDEN
The generated transmit pulse in channel x provides the appropriate pulse shape for line length from a DSX-1 cross connect through the setting of this register as shown below in Table 1. Loopback mode of channel x is activated through the setting of these registers as shown below in Table 2. This register as shown in Table 3 controls TIPx/RINGx output polarity. Initial value is "high". PDx is active-high to set the corresponding transceiver in power down mode. The impedance between TTIP and TRING is set to 30k(typ). LOSx goes "high" in power down mode. Initial value is "high". MSKx is active-high to prevent LOSx or LOTCx from setting INT output "high". Initial value is "high". RDEN is active-high to prevent RCLK, RPOS, and RNEG output from forcing to "low" or "high" by the detection of Loss of signal. Initial value is "low". 18 1999/9
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ASAHI KASEI
[AK2546]
Table 1. Pulse Shape Control
LENG3x 0 0 0 0 1 LENG2x 0 0 1 1 0 LENG1x 0 1 0 1 0 Line Length 0-133feet (Initial Value) 133-266feet 266-399feet 399-533feet 533-655feet
Table 2. Loopback mode Select
RLOOPx 0 0 1 1 LLOOPx 0 1 0 1 Normal Local Loop back Remote Loop back Inhibited Function (Initial value)
Table 3. TIPx/RINGx Polarity Control
POLNx 1 0 POSx/NEGx 0 1 0 1 TIPx/RINGx space mark mark space
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ASAHI KASEI
[AK2546]
OUTPUT CONTROL
*: don't care LOS: LOSx output and LOSx register
Reset, Loss of MCLK, Power down
RESET MCLK PD Loopback Local 0 1 1 1 1 * loss loss clocked clocked * * * 1 1 * * * * * Remote * * * * * * 1 0 1 0 * * * * * * * * * * POLN RDEN TCLK Receive signal * * * * * TTIP TRING 0(Note 1) 0 0 0(Note 1) 0(Note 1) 0 0 0 0 0 RCLK RPOS RNEG 0 0 1 0 1 1 1 1 1 1 LOS
Normal Operation(RESET=1, MCLK: Clocked, PD=0)
Loopback Local 0 Remote 0 1 * clocked POLN RDEN TCLK Receive signal in TTIP TRING TPOS TNEG 0 0 1 0 clocked loss TPOS TNEG 0 0 1 * loss in 0 RCLK RTIP RRING 0 0 0 0 1 1 0 1 loss clocked loss loss 0 TPOS TNEG 0 0 1 1 loss loss 0 RCLK 0 RCLK 0 RTIP RRING RTIP RRING 0 0 0 * clocked in TPOS TNEG 0 0 0 0 clocked loss TPOS TNEG 0 0 0 * loss in 0 RCLK RTIP RRING 0 0 0 0 0 0 0 1 loss clocked loss loss 0 TPOS TNEG 0 0 0 1 loss loss 0 RCLK 0 RCLK 1 RTIP RRING RTIP RRING 1 1 1 0 0 RCLK RTIP RRING 1 1 0 1 1 1 0 0 RCLK RCLK RPOS RNEG RTIP RRING 0 1 0 LOS
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ASAHI KASEI
[AK2546]
Remote Loopback(RESET=1, MCLK: Clocked, PD=0)
Loopback Local 0 Remote 1 1 * * POLN RDEN TCLK Receive signal in RRING RTIP 0 1 1 0 * loss RRING RTIP 0 1 1 1 * loss RRING RTIP 0 1 0 * * in RRING RTIIP 0 1 0 0 * loss RRING RTIP 0 1 0 1 * loss RRING RCLK RRING RTIP 1 0 1 1 RCLK RRING RCLK RRING RTIP 0 RTIP 1 0 0 1 TTIP TRING RTIP RCLK RRING RCLK RPOS RNEG RTIP 0 LOS
Local Loopback(RESET=1, MCLK: Clocked, PD=0)
Loopback Local 1 Remote 0 1 * clocked POLN RDEN TCLK Receive signal in TTIP TRING TPOS TNEG 1 0 1 * clocked loss TPOS TNEG 1 1 1 0 0 0 1 1 0 * * * loss loss clocked in loss in 0 0 TPOS TNEG 1 0 0 * clocked loss TPOS TNEG 1 1 0 0 0 0 * * loss loss in loss 0 0 TCLK (Note 2) TCLK (Note 2) 0 0 TCLK (Note 2) TCLK (Note 2) 0 0 RCLK RPOS RNEG TPOS TNEG TPOS TNEG 0 0 TPOS TNEG TPOS TNEG 1 1 0 1 1 0 1 0 1 0 LOS
Note 1) The impedance between TTIP and TRING is 30k(typ). Note 2) The phase of the TCLK satisfies receive output timing.
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ASAHI KASEI
[AK2546]
THEORY OF OPERATION
Loss of signal Loss of signal in channel x is reported by setting LOSx register "high". The receiver will indicate loss of signal upon receiving 175 consecutive zeros or detecting input level being below the threshold (ALOS). LOSx returns to "low" when the received signal returns to 12.5% ones density and not including 100 consecutive zeros. (GR-820)
When Loss of Signal is detected in channel x, LOSx register is set "high" and LOSx pin becomes "high". When LOSx is set "high", interrupt will be issued on INT pin if MLOSx is "low". LOSx pin becomes high regardless of MLOSx status. MLOSx is active-high and masks LOSx interrupt. LOSx registers and LOSx pins represent the current status of received signal regardless of the MLOSx status.
Loss of TCLK Loss of TCLKx is reported by setting LOTCx "high". When LOTCx is set "high", INT output becomes "high" if MLOTCx is "low". MLOTCx is active-high and masks LOTCx interrupt. LOTCx represents the current status of TCLKx and can be read regardless of MLOTCx status. When Loss of TCLKx is detected, TTIPx/TRINGx will be forced to "0". Loss of MCLK Loss of MCLK is reported by setting LOMC "high". When LOMC is set "high", INT output becomes "high" if MLOMC is "low". MLOMC is active-high and masks LOMC interrupt. LOMC represents the current status of MCLK and can be read regardless of MLOMC status. When the loss of MCLK is detected, LOSx register and LOSx pin goes "high" at the same time. Therefore all MLOSx register must be set to "high" to prevent loss of MCLK from setting INT output INT output INT output becomes "high" when the alarm is reported to any one of LOSx, LOTCx or LOMC registers. This pin can be masked by MLOSx, MLOTCx or MLOMC registers. Local Loopback In Local Loopback mode, TPOSx, TNEGx, TCLKx signals are looped back to RPOSx, RNEGx, RCLKx output. RTIPx, RRINGx inputs are ignored but loss of signal detection is active. The transmitter in channel x outputs TTIPx, TRINGx normally. Remote Loopback In Remote Loopback mode, RTIPx/RRINGx signals are looped back to TTIPx/TRINGx output. The receiver in channel x output RPOSx, RNEGx, RCLKx normally and detect loss of signal. TPOSx, TNEGx, TCLKx inputs are ignored.
C0019-E-01 22 1999/9
ASAHI KASEI
[AK2546]
RECOMMENDED EXTERNAL CIRCUIT
Transmit Circuit
VDD AK2546 TTIPx VDD C1 1:2
TRINGx C1=0.47F
Received Circuit
VDD AK2546 RTIPx R3 VDD RRINGx R1 2:1
R4
R2
R1=R2=68 R3=R4=130
Recommended Transformer Specification Turns Primary Leakage Ratio Inductance Inductance (Max) (Typ) (Min)
Tx Rx 1:2 1:2 720H 720H 0.3H 0.3H
Interwinding Capacitance (Max) 30pF 30pF
DCR (Max) pri 0.6 0.6
sec 1.2 1.2
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ASAHI KASEI
[AK2546]
Reference current circuit
To determine input reference current, connect 12k1% resistor. AK2546 R1 BGREF
R1=12k1%
Power Supply
To attenuate the power supply noise, connect capacitors between VDD and VSS respectively. The value of the capacitance AK2546 need depend on the condition of the power supply line. Please decide the value of the capacitance after your evaluation.
AK2546
VDD
C1
Pin name RAVDD1-RAVSS1, RAVDD2-RAVSS2, BVDD-BVSS, TAVDD1-TAVSS1, TAVDD2-TAVSS2 TVDD1-TVSS1, TVDD2-TVSS2, TVDD3-TVSS3, TVDD4-TVSS4, TVDD5-TVSS5, IOVSS1, PVDD-PVSS TVDD6-TVSS6, TVDD7-TVSS7, IOVDD1IOVDD2-IOVSS2, DVDD1-DVSS1, DVDD2-DVSS2,
C1 1F 0.01F
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ASAHI KASEI
[AK2546]
Recommended conditions for PCB board
For the performance of noise and heat, the board design must be taken care. Recommended conditions for PCB board is shown below. Recommended conditions: Multilayerboard with more than two VDD or GND layer Please design the rest of pattern for GND
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ASAHI KASEI
[AK2546]
PACKAGE
144pin LQFP OUTPUT DIMENSIONS
22.0 20.0 108 73
109
72
AK2546 XXXXXXX JAPAN
144 37
20.0 36
0.07
1.70 Max 1.40
1 0.50 0.20
0.10 M
0.17
0.04
22.0
0~10
0.10
0.10 0.500.1
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ASAHI KASEI
[AK2546]
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. As
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